A DRAM array is comprised of individual memory cells constructed on a lightly-doped silicon substrate which are arranged by columns and rows. Each cell has a field-effect access transistor and a storage capacitor. The capacitor, which is directly connected to the transistor's source or storage node, may be charged and discharged through the transistor's channel. Transistor gates and gate interconnects within an array row are formed from a ribbon of conductive material which runs the length of the row. This conductive ribbon is known as a row line. Between consecutive transistor gates with a row, the row line traverses a field oxide region. In active areas of the array (locations where the row line functions as a gate), the row line is insulated from the substrate by a layer of gate oxide. When voltage is applied to each row line through a driver transistor, the transistors within the row are turned on. The access node of each transistor within an array column is interconnected with a bit line. In order to determine the capacitor charge value (which may be equated with either a "1" or a "0" binary value), a column sense amp at the end of the bit line compares the capacitor charge to a reference voltage.
The speed of a dynamic random access memory is dependent on a number of factors. One of the primary factors is access speed--the speed at which a row line can turn on the transistors of the cells along a row. Row line access speed is inversely proportional to the rowline's RC (resistance multiplied by capacitance) constant. In other words, an increase in either the resistance or the capacitance of the rowline will degrade access speed. The reduction of rowline resistance is easily achieved. In fact, current DRAM designs typically utilize rowlines constructed from conductively-doped polycrystalline silicon (hereinafter also "polysilicon" or "poly") that has been silicided with a refractory metal such as titanium, platinum, palladium, cobalt or tungsten. The resistance of a silicided, conductively-doped polysilicon is generally within the range of 15-20 ohms per square, whereas the resistance of titanium silicided conductively-doped polysilicon, for example, is approximately 2 ohms per square. However, the reduction of row line capacitance is more problematic. Row line capacitance is roughly equal to the summation of the poly gate-to-substrate capacitances, since the field oxide regions are relatively thick and capacitances of the word line over these regions is relatively minimal. Using current production techniques, all transistors within a DRAM array (whether they be cell access transistors or transistors within the periphery) utilize a single thickness of gate oxide. In order to reduce row line capacitance using current fabrication techniques, it would be necessary to increase the gate oxide layer thickness. Since capacitance is inversely proportional to dielectric layer thickness, a doubling of dielectric layer thickness should approximately halve row line capacitance. However, the drive current at maximum voltage for the peripheral, rowline driver transistors is decreased by the increase in dielectric layer thickness. Since a reduction in drive current will result in a reduction in rowline access speed, the gain in speed achieved through the reduction in row line capacitance has been offset by the reduction in speed caused by decreased drive current.